The Ultra-High-Speed Flash Microcontroller User's Guide contains detailed information on features specific to Maxim's ultra-high-speed flash microcontrollers.
Maxim’s ultra-high-speed flash microcontroller is an 8051-compatible microcontroller that provides improved performance and power
consumption when compared to the original 8051 version. It retains instruction set and object code compatibility with the 8051, yet performs
the same operations in fewer clock cycles. Consequently, greater throughput is possible for the same crystal speed. As an alternative,
the device can be run at a reduced frequency to save power. The more efficient design allows a much slower crystal speed to
get the same results as an original 8051, using much less power.
The fundamental innovation of the ultra-high-speed flash microcontroller is the use of only one clock per instruction cycle compared
with 12 for the original 8051. This results in up to 12 times improvement in performance over the original 8051 architecture and up to
four times improvement over other Maxim high-speed microcontrollers. The device provides several peripherals and features in addition
to all of the standard features of an 80C32. These include 16kB/32kB/64kB of on-chip flash memory, 1kB of on-chip RAM, four 8-bit
I/O ports, three 16-bit timer/counters, two on-chip UARTs, dual data pointers, an on-chip watchdog timer, five levels of interrupt priority,
and a crystal multiplier. The device provides 256 bytes of RAM for variables and stack; 128 bytes can be reached using direct or indirect
addressing, or using indirect addressing only.
In addition to improved efficiency, it can operate at a maximum clock rate of 33MHz. Combined with the 12 times performance, this
allows for a maximum performance of 33 million instructions per second (MIPS). This level of computing power is comparable to many
16-bit processors, but without the added expense and complexity if implementing a 16-bit interface.
The device incorporates a power-management mode that allows the device to dynamically vary the internal clock speed from 1 clock
per cycle (default) to 1024 clocks per cycle. Because power consumption is directly proportional to clock speed, the device can reduce
its operating frequency during periods of little switchback. This greatly reduces power consumption. The switchback feature allows the
device to quickly return to highest speed operation upon receipt of an interrupt or serial port activity, allowing the device to respond to external events while in power-management mode.

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