--- 產(chǎn)品詳情 ---
Power switch | MOSFET, GaNFET |
Input VCC (Min) (V) | 4.5 |
Input VCC (Max) (V) | 5.5 |
Peak output current (A) | 5 |
Rise time (ns) | 7 |
Operating temperature range (C) | -40 to 125 |
Undervoltage lockout (Typ) | 4 |
Rating | Catalog |
Number of channels (#) | 2 |
Fall time (ns) | 3.5 |
Prop delay (ns) | 35 |
Iq (uA) | 90 |
Input threshold | TTL |
Channel input logic | TTL |
Negative voltage handling at HS pin (V) | -5 |
Features | Bootstrap supply voltage clamping, Split outputs on high and low side |
Driver configuration | Half Bridge |
- Independent High-Side and Low-Side
TTL Logic Inputs - 1.2-A Peak Source, 5-A Sink Current
- High-Side Floating Bias Voltage Rail
Operates up to 100 VDC - Internal Bootstrap Supply Voltage Clamping
- Split Outputs for Adjustable
Turnon, Turnoff Strength - 0.6-? Pulldown, 2.1-? Pullup Resistance
- Fast Propagation Times (35 ns Typical)
- Excellent Propagation Delay Matching
(1.5 ns Typical) - Supply Rail Undervoltage Lockout
- Low Power Consumption
The LMG1205 is designed to drive both the high-side and the low-side enhancement mode Gallium Nitride (GaN) FETs in a synchronous buck, boost, or half-bridge configuration. The device has an integrated 100-V bootstrap diode and independent inputs for the high-side and low-side outputs for maximum control flexibility. The high-side bias voltage is generated using a bootstrap technique and is internally clamped at 5 V, which prevents the gate voltage from exceeding the maximum gate-source voltage rating of enhancement mode GaN FETs. The inputs of the LMG1205 are TTL logic compatible and can withstand input voltages up to 14 V regardless of the VDD voltage. The LMG1205 has split-gate outputs, providing flexibility to adjust the turnon and turnoff strength independently.
In addition, the strong sink capability of the LMG1205 maintains the gate in the low state, preventing unintended turnon during switching. The LMG1205 can operate up to several MHz. The LMG1205 is available in a 12-pin DSBGA package that offers a compact footprint and minimized package inductance.
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