| Topology | Boost, Flyback, Forward, Full-Bridge, Half-Bridge, Push-Pull |
| Duty cycle (Max) (%) | 50 |
| Vin (Max) (V) | 22 |
| UVLO thresholds on/off (V) | 9.2/8.4 |
| Features | Error Amplifier, Leading Edge Blanking, Multi-topology, Soft Start, Synchronization Pin |
| Operating temperature range (C) | -40 to 125 |
| Switching frequency (Max) (kHz) | 1000 |
| Rating | Automotive |
| Gate drive (Typ) (A) | 2 |
- Qualified for Automotive Applications
- Improved Version of the UC3825 PWM
- Compatible With Voltage-Mode or Current-Mode Control Methods
- Practical Operation at Switching Frequencies to 1 MHz
- 50-ns Propagation Delay to Output
- High-Current Dual Totem-Pole Outputs: 2 A (Peak)
- Trimmed Oscillator Discharge Current
- Low 100-μA Startup Current
- Pulse-by-Pulse Current-Limiting Comparator
- Latched Overcurrent Comparator With Full-Cycle Restart
The UC2825A pulse-width modulation (PWM) controller is an improved versions of the standard UC3825. Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is 12 MHz, while input offset voltage is 2 mV. Current limit threshold is specified to a tolerance of 5%. Oscillator discharge current is specified at 10 mA for accurate dead-time control. Frequency accuracy is improved to 6%. Startup supply current, typically 100 μA, is ideal for off-line applications. The output drivers are redesigned to actively sink current during undervoltage lockout (UVLO) at no expense to the startup current specification. In addition, each output is capable of 2-A peak currents during transitions.
Functional improvements have also been implemented. The shutdown comparator is now a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency does not exceed the designed soft start period. The CLOCK pin has become CLK/LEB. This pin combines the functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing.
The UC2825A has dual alternating outputs and the same pin configuration of the UC3825. "A" version parts have UVLO thresholds identical to the original UC3825.
See the application report, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers (SLUA125) for detailed technical and application information.
