VHDL語言設(shè)計(jì)四人搶答器方案三

問題描述

設(shè)計(jì)一個(gè)4人參加的智力競賽搶答計(jì)時(shí)器。電路具有回答問題時(shí)間控制功能。要求回答問題時(shí)間小于等于100妙（顯示為0～99），時(shí)間顯示采用倒計(jì)時(shí)方式。當(dāng)達(dá)到限定時(shí)間時(shí)，發(fā)出聲響以示警告；當(dāng)有某一參賽者首先按下?lián)尨痖_關(guān)時(shí)，相應(yīng)顯示燈亮并伴有聲響，此時(shí)搶答器不再接受其他輸入信號(hào)。

功能要求

1、用feng模塊將選手按下按鍵信號(hào)輸出高電平給鎖存模塊lockb，進(jìn)行鎖存的同時(shí)發(fā)出aim信號(hào)實(shí)現(xiàn)聲音提示，并使count模塊進(jìn)行答題時(shí)間的倒計(jì)時(shí)，在計(jì)滿100妙后送出聲音提示；

2、用ch41a模塊將搶答結(jié)果轉(zhuǎn)換為二進(jìn)制數(shù)；

3、用sel模塊產(chǎn)生數(shù)碼管片選信號(hào)；

4、用ch42a模塊將對(duì)應(yīng)數(shù)碼管片選信號(hào)，送出需要的顯示信號(hào)；

5、用七段譯碼器dispa模塊進(jìn)行譯碼。

各模塊VHDL源代碼

1、搶答鑒別模塊FENG的VHDL源程序

--feng.vhd

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY FENG IS

PORT（CP，CLR:IN STD_LOGIC;

Q ：OUT STD_LOGIC）;

END FENG;

ARCHITECTURE FENG_ARC OF FENG IS

BEGIN

PROCESS（CP，CLR）

BEGIN

IF CLR=‘0’THEN

Q<=‘0’;

ELSIF CP‘EVENT AND CP=’0‘THEN

Q<=’1‘;

END IF;

END PROCESS;

END FENG_ARC;

2、片選信號(hào)產(chǎn)生模塊SEL的VHDL源程序

--sel.vhd

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY SEL IS

PORT（CLK:IN STD_LOGIC;

a:OUT INTEGER RANGE 0 TO 7）;

END SEL;

ARCHITECTURE SEL_ARC OF SEL IS 片選信號(hào)產(chǎn)生模塊SEL

BEGIN

PROCESS（CLK）

VARIABLE AA:INTEGER RANGE 0 TO 7;

BEGIN

IF CLK’EVENT AND CLK=‘1’THEN

AA：=AA+1;

END IF;

A<=AA;

END PROCESS;

END SEL_ARC;

3、鎖存器模塊LOCKB的VHDL源程序

-lockb.vhd

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY LOCKB IS

PORT（D1，D2，D3，D4:IN STD_LOGIC;

CLK，CLR:IN STD_LOGIC;

Q1，Q2，Q3，Q4，ALM:OUT STD_LOGIC）;

END LOCKB;

ARCHITECTURE LOCK_ARC OF LOCKB IS

BEGIN

PROCESS（CLK）

BEGIN

IF CLR=‘0’THEN

Q1<=‘0’;

Q2<=‘0’;

Q3<=‘0’;

Q4<=‘0’;

ALM<=‘0’; 模塊LOCKB

ELSIF CLK‘EVENT AND CLK=’1‘THEN

Q1<=D1;

Q2<=D2;

Q3<=D3;

Q4<=D4;

ALM<=’1‘;

END IF;

END PROCESS;

END LOCK_ARC;

4、轉(zhuǎn)換模塊CH41A的VHDL源程序

--ch41a..vhd

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY CH41A IS

PORT（D1，D2，D3，D4:IN STD_LOGIC;

Q:OUT STD_LOGIC_VECTOR（3 DOWNTO 0））;

END CH41A;

ARCHITECTURE CH41_ARC OF CH41A IS 轉(zhuǎn)換模塊CH41A

BEGIN

PROCESS（D1，D2，D3，D4）

VARIABLE TMP:STD_LOGIC_VECTOR（3 DOWNTO 0）;

BEGIN

TMP：=D1&D2&D3&D4;

CASE TMP IS

WHEN “0111”=>Q<=“0001”;

WHEN “1011”=>Q<=“0010”;

WHEN “1101”=>Q<=“0011”;

WHEN “1110”=>Q<=“0100”;

WHEN OTHERS=>Q<=“1111”;

END CASE;

END PROCESS;

END CH41_ARC;

5、3選1模塊CH31A的VHDL源程序

--ch31a.vhd

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY CH31A IS

PORT（SEL:IN STD_LOGIC_VECTOR（2 DOWNTO 0）;

D1，D2，D3:IN STD_LOGIC_VECTOR（3 DOWNTO 0）;

Q ： OUT STD_LOGIC_VECTOR（3 DOWNTO 0））;

END CH31A;

ARCHITECTURE CH31_ARC OF CH31A IS

BEGIN

PROCESS（SEL，D1，D2，D3）

BEGIN

CASE SEL IS

WHEN “000”=>Q<=D1;

WHEN “001”=>Q<=D2;

WHEN “111”=>Q<=D3;

WHEN OTHERS=>Q<=“1111”;

END CASE;

END PROCESS;

END CH31_ARC;

6、倒計(jì)時(shí)模塊COUNT的VHDL源程序

倒計(jì)時(shí)模塊COUNT如圖16-7所示，該模塊實(shí)現(xiàn)答題時(shí)間的倒計(jì)時(shí)，在計(jì)滿100s后送出聲音提示。

--count.vhd

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY COUNT IS

PORT（CLK，EN:IN STD_LOGIC; 倒計(jì)時(shí) 模塊COUNT

H，L:OUT STD_LOGIC_VECTOR（3 DOWNTO 0）;

SOUND:OUT STD_LOGIC）;

END COUNT;

ARCHITECTURE COUNT_ARC OF COUNT IS

BEGIN

PROCESS（CLK，EN）

VARIABLE HH，LL:STD_LOGIC_VECTOR（3 DOWNTO 0）;

BEGIN

IF CLK’EVENT AND CLK=‘1’THEN

IF EN=‘1’THEN

IF LL=0 AND HH=0 THEN

SOUND<=‘1’;

ELSIF LL=0 THEN

LL：=“1001”;

HH：=HH-1;

ELSE

LL：=LL-1;

END IF;

ELSE

SOUND<=‘0’;

HH：=“1001”;

LL：=“1001”;

END IF;

END IF;

H<=HH;

L<=LL;

END PROCESS;

END COUNT_ARC;

7、顯示譯碼模塊DISP的VHDL源程序

--disp.vhd

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY DISP IS 顯示譯碼模塊DISP

PORT（D:IN STD_LOGIC_VECTOR（3 DOWNTO 0）;

Q:OUT STD_LOGIC_VECTOR（6 DOWNTO 0））;

END DISP;

ARCHITECTURE DISP_ARC OF DISP IS

BEGIN

PROCESS（D）

BEGIN

CASE D IS

WHEN“0000”=>Q<=“0111111”;

WHEN“0001”=>Q<=“0000110”;

WHEN“0010”=>Q<=“1011011”;

WHEN“0011”=>Q<=“1001111”;

WHEN“0100”=>Q<=“1100110”;

WHEN“0101”=>Q<=“1101101”;

WHEN“0110”=>Q<=“1111101”;

WHEN“0111”=>Q<=“0100111”;

WHEN“1000”=>Q<=“1111111”;

WHEN“1001”=>Q<=“1101111”;

WHEN OTHERS=>Q<=“0000000”;

END CASE;

END PROCESS;

END DISP_ARC;