白皮書下載鏈接：Arm架構(gòu)下的Synchronization概述和案例分析

https://developer.arm.com/documentation/107630/latest/

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1. 簡介

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隨著近年來Arm服務(wù)器的應(yīng)用越來越廣泛，越來越多的云廠商開始提供基于Arm架構(gòu)的云實(shí)例，越來越多的開發(fā)人員正在為Arm平臺編寫軟件。

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Synchronization是軟件遷移和優(yōu)化過程中的熱門話題。基于Arm架構(gòu)的服務(wù)器通常具有比其他架構(gòu)更多的CPU內(nèi)核，對Synchronization的深入理解顯得更為重要。

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Arm和X86 CPU之間最顯著的區(qū)別之一是它們的內(nèi)存模型：Arm架構(gòu)具有與x86架構(gòu)的TSO（Total Store Order）模型不同的弱內(nèi)存模型。不同的內(nèi)存模型可能會導(dǎo)致程序在一種架構(gòu)上運(yùn)行良好，但在另一種架構(gòu)上會遇到性能問題或錯誤。Arm服務(wù)器更寬松的內(nèi)存模型允許更多的編譯器和硬件優(yōu)化以提高系統(tǒng)性能，但代價是它更難理解并且可能更容易編寫錯誤代碼。

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我們創(chuàng)作此文檔是為了分享有關(guān)Arm架構(gòu)的Synchronization專業(yè)知識，可以幫助其他架構(gòu)的開發(fā)人員在Arm系統(tǒng)上進(jìn)行開發(fā)。

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2. Armv8-A架構(gòu)上的Synchronization方法

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本文檔首先介紹了Armv8-A架構(gòu)上的Synchronization相關(guān)知識，包括原子操作、Arm內(nèi)存順序和數(shù)據(jù)訪問屏障指令。

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2.1 原子操作

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鎖的實(shí)現(xiàn)要求原子訪問，Arm架構(gòu)定義了兩種類型的原子訪問：

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• Load exclusive and store exclusive

• Atomic operation, which is introduced in armv8.1-a large system extension (LSE)

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2.1.1 Exclusive load and store

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2.1.2 LSE Atomic operation

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• Compare and Swap instructions, CAS, and CASP. These instructions perform a read from memory and compare it against the value held in the first register. If the comparison is equal, the value in the second register is written to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write.

• Atomic memory operation instructions, LD, and ST, where is one of ADD, CLR, EOR, SET, SMAX, SMIN, UMAX, and UMIN. Each instruction atomically loads a value from memory, performs an operation on the values, and stores the result back to memory. The LD instructions save the originally read value in the destination register of the instruction.

• Swap instruction, SWP. This instruction atomically reads a location from memory into a register and writes back a different supplied value back to the same memory location.

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2.2 Arm內(nèi)存順序

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2.3 Arm數(shù)據(jù)訪問屏障指令

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• Does not guarantee when the operations happen, just guarantee the order

   LDR  X0, [X1]        ;Must be seen by memory system before STR
   DMB  SY
   ADD  X2, #1        ; May be executed before or after memory system sees LDR
   STR  X3, [X4]        ;Must be seen by memory system after LDR

• Use a DSB when necessary, but do not overuse them

• All explicit memory accesses before the DSB in program order have completed

• Any outstanding cache/TLB/branch predictor operations complete

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  DC   ISW        ; Operation must have completed before DSB can complete
  STR  X0, [X1]    ; Access must have completed before DSB can complete
  DSB  SY
  ADD  X2, X2, #3    ;Cannot be executed until DSB completes

• All accesses after the LDAR are observed by memory system after the LDAR.

• Accesses before the LDAR are not affected.

  

• All accesses before the STLR are observed by memory system before the STLR

• Accesses after the STLR are not affected

  

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3. C++內(nèi)存模型

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4. 總結(jié)

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參考文獻(xiàn)

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1. Arm, “Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile Documentation”?

   https://developer.arm.com/docs/ddi0487/latest

2. “The software suite diy7”
   http://diy.inria.fr/

3. “A working example of how to use the herd7 Memory Model Tool”https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/how-to-use-the-memory-model-tool
4. “How to generate litmus tests automatically with the diy7 tool”https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/generate-litmus-tests-automatically-diy7-tool
5. “Running litmus tests on hardware using litmus7”
   https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/running-litmus-tests-on-hardware-litmus7