實時：關于微控制器中斷等待時間的一些注釋

　　中斷需要大量的高速處理器，特別是大量流水線的處理器，每個周期能夠發(fā)出多條指令。在任何一次飛行中都可能有八到十個指令，要么必須運行到完成，要么在正常執(zhí)行恢復后取消并重新啟動。

　　電氣工程師需要檢查中斷對應用程序的響應是否足夠快，并且中斷的開銷不會淹沒主應用程序。

　　一個給定的MCU執(zhí)行中斷的速度有多快？這肯定會受到應用程序的影響，但是對于這個項目來說，找到一個數(shù)字似乎是不合理的。

　　當中斷發(fā)生時，CPU保存一些寄存器并執(zhí)行中斷服務例程（ISR），然后返回就緒狀態(tài)中的最高優(yōu)先級任務。中斷通常屏蔽和嵌套。

　　明確地說，延遲通常被指定為中斷請求和中斷服務例程中第一個指令的執(zhí)行之間的時間。然而，“真正的延遲”必須包括一些必須在ISR中完成的內務處理，這會導致混亂。

　　The value in which an electrical engineer is usually interested is the worst -case interrupt latency. This is a sum of many different smaller delays.

　　The interrupt request signal needs to be synchronized to the CPU clock. Depending on the synchronization logic， typically up to three CPU cycles can be lost before the interrupt request has reached the CPU core.

　　The CPU will typically complete the current instruction. This instruction can take a lot of cycles， with divide， push-multiple， or memory-copy instructions requiring most clock cycles taking the most time. There are often additional cycles required for memory access. In an ARM7 system， for example， the instruction STMDB SP！，{R0-R11，LR} （Push parameters and perm.） Registers is typically the worst case instruction. It stores 13 32-bit registers on the stack and requires 15 clock cycles.

　　The memory system may require additional cycles for wait states.

　　After completion of the current instruction， the CPU performs a mode switch or pushes registers （typically PC and flag registers） on the stack. In general， modern CPUs （such as ARM） perform a mode switch， which requires less CPU cycles than saving registers.

　　If your CPU is pipelined， the mode switch has flushed the pipeline and a few more cycles are required to refill it. But we are not done yet. In more complex systems， there can be additional causes for interrupt latencies.