MM54HC137/MM74HC137 3-to-8 Line
Decoder With Address Latches
(Inverted Output)
General Description
This device utilizes advanced silicon-gate CMOS technology,
to implement a three-to-eight line decoder with latches
on the three address inputs. When GL goes from low to
high, the address present at the select inputs (A, B and C) is
stored in the latches. As long as GL remains high no address
changes will be recognized. Output enable controls,
G1 and G2, control the state of the outputs independently of
the select or latch-enable inputs. All of the outputs are high
unless G1 is high and G2 is low. The HC137 is ideally suited
for the implementation of glitch-free decoders in stored-address
applications in bus oriented systems.
The 54HC/74HC logic family is speed, function and pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
diodes to VCC and ground.
Features
Y Typical propagation delay: 20 ns
Y Wide supply range: 2±6V
Y Latched inputs for easy interfacing.
Y Fanout of 10 LS-TTL loads.