The STWD100 watchdog timer circuits are self-contained devices which prevent system
failures that are caused by certain types of hardware errors (non-responding peripherals,
bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).
The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). The
input is used to clear the internal watchdog timer periodically within the specified timeout
period, twd (see Section 3: Watchdog timing). While the system is operating correctly, it
periodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is not
reset, a system alert is generated and the watchdog output, WDO, is asserted (see
Section 3: Watchdog timing).
The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable or
disable the watchdog functionality. The EN pin is connected to the internal pull-down
resistor. The device is enabled if the EN pin is left floating.

Features
■ Current consumption 13 μA typ.
■ Available watchdog timeout periods are
3.4 ms, 6.3 ms, 102 ms and 1.6 s
■ Chip-enable input
■ Open drain or push-pull WDO output
■ Operating temperature range: –40 to +125 °C
■ Package SOT23-5, SC70-5 (SOT323-5)