資料介紹
The SN74AUP1T87 performs the Boolean function Y = A ⊕ B with designation for logic-level translation applications with output referenced to supply VCC.
AUP technology is the industry’s lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity (see Figure 1 and Figure 2).
The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.
Schmitt-trigger inputs (
VT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.
Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.
The SN74AUP1T87 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
- SN74AUP1T98,pdf(Single-Supply
- SN74AUP1T97,pdf(Single-Supply
- SN74AUP1T58,pdf(Single-Supply
- SN74AUP1T57,pdf(Single-Supply
- SN74AUP1T86,pdf(Low Power, 1.8
- SN74AUP1T32,pdf(Low Power, 1.8
- SN74AUP1T17,pdf(Low Power, 1.8
- SN74AUP1T158,pdf(Low Power, 1.
- SN74AUP1T157,pdf(Low Power, 1.
- SN74AUP1T14,pdf(Low Power, 1.8
- SN74AUP1T08,pdf(Low Power, 1.8
- SN74AUP1T04,pdf(Low Power, 1.8
- SN74AUP1T02,pdf(Low Power, 1.8
- SN74AUP1T00,pdf(Low Power, 1.8
- SN74AUP1G74,pdf(Low-Power Sing
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