使用智能外設(shè)提高CPU效率

　　現(xiàn)代微控制器添加了一個范圍廣泛的新功能，在正確使用時可以大大提高應(yīng)用效率。特別是，可以使用獨立于CPU獨立操作的智能外設(shè)和外圍設(shè)備，允許CPU并行執(zhí)行其他任務(wù)，或者進入低功耗睡眠模式。使用這兩種技術(shù)都將提高整體處理效率和節(jié)約能源。

　　DMA控制器

　　在基于MCU的設(shè)計中遇到的第一個智能外設(shè)之一是直接存儲器存?。―MA）控制器。這個專用硬件塊可以在內(nèi)存和/或外設(shè)之間傳輸數(shù)據(jù)，而不需要CPU與每個傳輸相關(guān)。先進的DMA控制器，如包括對意法半導(dǎo)體STM32F4的家庭，可以進一步減少CPU的使用功能靈活的數(shù)據(jù)流分配和轉(zhuǎn)移管理。讓我們更詳細地看看其中的一些特性，看看它們?nèi)绾伪挥脕硖岣咛幚硇省?/p>

　　Figure 1 shows a block diagram representing the variety of data paths available in one of the two DMA controllers on STM32F4 devices. As shown on the left side of the figure， DMA requests originate from eight different channels （allocated to the various DMA-enabled peripherals） and are routed to eight different request inputs on the arbiter， establishing a priority （lower-numbered inputs have higher priority）。 The highest-priority transfer is then activated， and the AHB Masters， on the right side of the figure， execute the desired data transfer. Separate masters for both the memory and the peripheral interfaces further improve efficiency for peripheral-to-memory transfers， probably the most prevalent use of a DMA in MCU-based designs.

　　The allocation of separate FIFOs for each stream， as shown in the middle of Figure 1， allows the FIFO characteristics to be tuned for each peripheral interface’s characteristics. For example， the threshold level of the FIFO （depth at which a transfer is requested） can be individually set at ?， ?， or ? of the FIFO size. This allows lower-speed channels to wait until the FIFO is almost full before a transfer to minimize overhead. Faster channels would initiate a transfer sooner， perhaps at ? the size to avoid a FIFO overrun.