• AD7490

• EVAL-AD7490SDZ

This document presents the steps to setup an environment for using the EVAL-AD7490SDZ evaluation board together with the Xilinx KC705 FPGA board and the Xilinx Embedded Development Kit (EDK). Below is presented a picture of the EVAL-AD7490SDZ Evaluation Board with the Xilinx KC705 board.

Below is presented a picture of SDP-B Controller Board with the EVAL-AD7490SDZ Evaluation Board.

The EVAL-AD7490SDZ evaluation board is a member of a growing number of boards available for the SDP. It was designed to help customers evaluate performance or quickly prototype new AD7490 circuits and reduce design time.

The AD7490 is a 12-bit high speed, low power, successive- approximation ADC. The part operates from a single 2.7 V to 5.25 V power supply and features throughput rates up to 1 MSPS. The part contains a low-noise, wide bandwidth track/hold amplifier that can handle input frequencies in excess of 1 MHz.

• AD7490 Product Info - pricing, samples, datasheet
• EVAL-AD7490SDZ evaluation board user guide is included on the CD as part of the Evaluation Board Kit
• Xilinx KC705 FPGA board

The first objective is to ensure that you have all of the items needed and to install the software tools so that you are ready to create and run the evaluation project.

• Xilinx KC705 FPGA board rev C
• FMC-SDP adapter board
• EVAL-AD7490SDZ evaluation board

• Xilinx ISE 14.3
• A UART terminal (ex. TeraTerm / Hyperterminal).

• Reference Design Files

The following table presents a short description the reference design archive contents.

• Use the FMC-SDP interposer to connect the ADI evaluation board to the Xilinx KC705 board on the FMC LPC connector.
• Connect the JTAG and UART cables to the KC705 and power up the FPGA board.
• Start IMPACT, and double click “Boundary Scan”. Right click and select Initialize Chain. The program should recognize the Kintex 7 device (see screenshot below).

• Program the KC705 FPGA using the “Bit/download.bit” file provided in the reference design archive.
• Power the ADI evaluation board.
• Start a UART terminal and set the baud rate to 115200 bps.

At this point everything is set up and it is possible to start the evaluation of the ADI hardware. To capture data from the ADC run the data_capture.bat script located in the DataCapture folder from the reference design .zip file. Every time the script is run a new batch of 8192 samples are read from the ADC at the ADC's maximum sampling rate and saved into the Acquisition.csv file located in the same folder as the data capture script. The data_capture.tcl file can be modified for different configuration words to be programmed on the AD7490. On the UART terminal messages will be displayed to show the status of the program running on the FPGA as shown in the picture below.

If the resulting csv file is opened with Microsoft Excel, the data will be displayed on a different number of columns, each column corresponding to a channel.