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OMAP3503 應(yīng)用處理器

數(shù)據(jù)： OMAP3515/03 Applications Processor 數(shù)據(jù)表

描述

設(shè)備基于增強(qiáng)型OMAP 3架構(gòu)。

OMAP 3架構(gòu)旨在提供一流的視頻，圖像和圖形處理足以支持以下內(nèi)容：

流媒體視頻
視頻會(huì)議
高分辨率靜止圖像

該設(shè)備支持高級(jí)操作系統(tǒng)（HLOS），例如：

Linux®
Windows®CE
Android ™

此OMAP設(shè)備包括高性能移動(dòng)產(chǎn)品所需的最先進(jìn)的電源管理技術(shù)。

以下子系統(tǒng)是設(shè)備的一部分：

基于ARM Cortex-A8微處理器的微處理器單元（MPU）子系統(tǒng)
用于支持顯示的3D圖形加速的PowerVR SGX子系統(tǒng)（僅限OMAP35設(shè)備）
支持多種格式的相機(jī)圖像信號(hào)處理器（ISP）和連接到各種圖像傳感器的接口選項(xiàng)

顯示子系統(tǒng)具有多種并發(fā)圖像處理功能，以及支持各種顯示器的可編程接口。顯示子系統(tǒng)還支持NTSC和PAL視頻輸出。

3級(jí)（L3）和4級(jí)（L4）互連，為多個(gè)啟動(dòng)器提供高帶寬數(shù)據(jù)傳輸?shù)絻?nèi)部和外部存儲(chǔ)器控制器以及打開(kāi)芯片外設(shè)

該器件還提供：

全面的電源和時(shí)鐘管理方案，可實(shí)現(xiàn)高性能，低功耗運(yùn)行，以及超低功耗待機(jī)功能。該器件還支持SmartReflex自適應(yīng)電壓控制。這種用于自動(dòng)控制模塊工作電壓的電源管理技術(shù)可降低有功功耗。
使用封裝上封裝（POP）實(shí)現(xiàn)的存儲(chǔ)器堆疊功能（僅限CBB和CBC封裝）

OMAP35器件采用515引腳s-PBGA封裝（CBB后綴），515引腳s-PBGA封裝（CBC后綴）和423引腳s-PBGA封裝（CUS后綴）。 CUS包中沒(méi)有CBB和CBC包的某些功能。（有關(guān)封裝差異，請(qǐng)參見(jiàn)表1-1）。

本數(shù)據(jù)手冊(cè)介紹了OMAP35應(yīng)用處理器的電氣和機(jī)械規(guī)格。除非另有說(shuō)明，否則本數(shù)據(jù)手冊(cè)中的信息適用于OMAP35應(yīng)用處理器的商用和擴(kuò)展溫度版本。本數(shù)據(jù)手冊(cè)由以下部分組成：

第2節(jié)：端子描述：分配，電氣特性，多路復(fù)用和功能描述
第3節(jié)：電氣特性：電源域，工作條件，功耗和直流特性
第4節(jié)：時(shí)鐘規(guī)范輸入和輸出時(shí)鐘，DPLL和DLL
第5節(jié)：視頻Dac規(guī)范
第6節(jié)：時(shí)序要求和開(kāi)關(guān)特性
第7節(jié)：封裝特性：可用封裝的熱特性，器件命名和機(jī)械數(shù)據(jù)

特性

OMAP3 Devices:
- OMAP™ 3 Architecture
- MPU Subsystem
  - Up to 720-MHz ARM® Cortex™-A8 Core
  - NEON™ SIMD Coprocessor
- PowerVR® SGX™ Graphics Accelerator
  - Tile-Based Architecture Delivering up to 1 MPoly/sec
  - Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
  - Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
  - Fine-Grained Task Switching, Load Balancing, and Power Management
  - Programmable High-Quality Image Anti-Aliasing
- Fully Software-Compatible with ARM9™
- Commercial and Extended Temperature Grades
ARM Cortex-A8 Core
- ARMv7 Architecture
  - TrustZone®
  - Thumb®-2
  - MMU Enhancements
- In-Order, Dual-Issue, Superscalar Microprocessor Core
- NEON Multimedia Architecture
- Over 2x Performance of ARMv6 SIMD
- Supports Both Integer and Floating-Point SIMD
- Jazelle® RCT Execution Environment Architecture
- Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
- Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
ARM Cortex-A8 Memory Architecture:
- -KB Instruction Cache (4-Way Set-Associative)
- -KB Data Cache (4-Way Set-Associative)
- -KB L2 Cache
112KB of ROM
64KB of Shared SRAM
Endianess:
- ARM Instructions – Little Endian
- ARM Data – Configurable
External Memory Interfaces:
- General Purpose Memory Controller (GPMC)
  - 16-Bit-Wide Multiplexed Address and Data Bus
  - Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
  - Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
  - Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
  - Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
Camera Image Signal Processor (ISP)
- CCD and CMOS Imager Interface
- Memory Data Input
- BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
- Glueless Interface to Common Video Decoders
- Resize Engine
  - Resize Images From 1/4x to 4x
  - Separate Horizontal and Vertical Control
Display Subsystem
- Parallel Digital Output
  - Up to 24-Bit RGB
  - HD Maximum Resolution
  - Supports Up to 2 LCD Panels
  - Support for Remote Frame Buffer Interface (RFBI) LCD Panels
- 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
  - Composite NTSC and PAL Video
  - Luma and Chroma Separate Video (S-Video)
- Rotation 90-, 180-, and 270-Degrees
- Resize Images From 1/4x to 8x
- Color Space Converter
- 8-Bit Alpha Blending
Serial Communication
- 5 Multichannel Buffered Serial Ports (McBSPs)
  - 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
  - 5-KB Transmit and Receive Buffer (McBSP2)
  - SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
  - Direct Interface to I2S and PCM Device and TDM Buses
  - 128-Channel Transmit and Receive Mode
- Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
- High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
- High-, Full-, and Low-Speed Multiport USB Host Subsystem
  - 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
- One HDQ™/1-Wire® Interface
- UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
- Three Master and Slave High-Speed Inter-Integrated Circuit (I²C) Controllers
Removable Media Interfaces:
- Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
Comprehensive Power, Reset, and Clock Management
- SmartReflex™ Technology
- Dynamic Voltage and Frequency Scaling (DVFS)
Test Interfaces
- IEEE 1149.1 (JTAG) Boundary-Scan Compatible
- ETM Interface
- Serial Data Transport Interface (SDTI)
12 32-Bit General-Purpose Timers
2 32-Bit Watchdog Timers
1 32-Bit 32-kHz Sync Timer
Up to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
5-nm CMOS Technologies
Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
Discrete Memory Interface
Packages:
1.8-V I/O and 3.0-V (MMC1 Only),

Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.