The CD4034BM/CD4034BC is an 8-bit CMOS static shift
register with two parallel bidirectional data ports (A and B)
which, when combined with serial shifting operations, can
be used to (1) bidirectionally transfer parallel data between
two buses, (2) convert serial data to parallel form and direct
them to either of two buses, (3) store (recirculate) parallel
data, or (4) accept parallel data from either of two buses
and convert them to serial form. These operations are controlled
by five control inputs:
A ENABLE (AE): ``A'' data port is enabled only when AE
is at logical ``1''. This allows the use of a common bus
for multiple packages.
A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B): This input
controls the direction of data flow. When at logical `'1'',
data flows from port A to B (A is input, B is output).
When at logical ``0'', the data flow direction is reversed.
ASYNCHRONOUS/SYNCHRONOUS (A/S): When A/S
is at logical ``0'', data transfer occurs at positive transition
of the CLOCK. When A/S is at logical ``1'', data
transfer is independent of the CLOCK for parallel operation.
In serial mode, A/S input is internally disabled such
that operation is always synchronous. (Asynchronous
serial operation is not possible.)
PARALLEL/SERIAL (P/S): A logical ``1'' P/S input allows
data transfer into the registers via A or B port (synchronous
if A/S e logical ``0'', asynchronous if A/S e
logical ``1''). A logical ``0'' P/S allows serial data to
transfer into the register synchronously with the positive
transition of the CLOCK, independent of the A/S input.
CLOCK: Single phase, enabled only in synchronous
mode. (Either P/S e logical ``1'' and A/S e logical ``0''
or P/S e logical ``0''.
All register stages are D-type master-slave flip-flops with
separate master and slave clock inputs generated internally
to allow synchronous or asynchronous data transfer from
master to slave.
All inputs are protected against damage due to static discharge
by diode clamps to VDD and VSS.