CrowdSupply剛上線一個眾籌項目 - 稱之為Precursor的便攜式、開源RISC-V SoC開發(fā)套件，使用了分別來自Xilinx和Lattice的兩顆流行的FPGA。

從外觀上看，它像極了一個智能手機(jī)，它號稱，通過編程，你確實可以把它當(dāng)成一個智能手機(jī)或平板電腦使用，且你可以對它有完全的控制，因為你可以編程它的每一個bit，沉到硬件的最底層！

套件的正面照片

背面照片

拆開了由以下一些部分組成：

一塊電路板

一個單色的LCD屏

一個鍵盤

看看鍵盤的電路板：

內(nèi)部的結(jié)構(gòu)：

高度安全、完全可信任

從下面的對比圖中可以看到其主要的功能：

再跟其它的FPGA開發(fā)板比較一下：

價格高是有原因的。

下面是其結(jié)構(gòu)框圖：

功能特性：

Made for developers

No adhesives holding the bezels in place – just one screw driver is all it takes

Want to add hardware? Maybe a cellular modem? No problem!

Battery compartment is a blank check for your peripherals

Install a smaller battery for more space

Flex PCB breakout for 8x FPGA GPIO into the battery compartment

Bezel is made out of FR-4, and can be user-customized to hold additional components

Inspect, modify and compile your SoC and embedded controller from source

All source fileshosted on GitHubfor convenient fork, pull request, and issue tracking

Open source PCB and case design

Easy-access developer's cable (included)

Low-level debugging (GDB + Chipscope) and firmware flashing via developer's cable plugged into a custom Raspberry Pi HAT (included)

Middleware debugging via USB cable via wishbone tunnel

Open source to the core

Extendable and modifiable

Slim and light mobile form factor

6063 alloy aluminum case -– 3D files provided, so you can mill your own case!

FR-4 front bezel -– PCB source provided

ABS + PC polymer antenna radome -– 3D printable

69 mm x 138 mm x 7.2 mm

96 grams reference weight

Compare to iPhone X at 70.9 mm x 143.6 mm x 7.7 mm and 174 grams

Accessible mechanical design

User-customizable CPUs

Manages power, standby, and charging functions

Tested with 18 MHz VexRISC-V, RV32I, no cache

-L1 speed grade for longer battery life

Tested with 100 MHz VexRISC-V, RV32IMAC + MMU, 4k L1 I/D cache

Xilinx XC7S50 primary System on Chip (SoC) FPGA

iCE40UP5K secondary Embedded Controller (EC) FPGA

16 MB external SRAM

128 MB Flash

100 MHz DDR 8-bit wide bus for fast XIP code performance

Dual hardware TRNG

External discrete noise generator

In-SoC ring oscillator based TRNG

Inspectable I/O

Physical keyboard with changeable layout overlays

200 ppi black and white LCD (336 x 536 resolution), 100% inspectable with standard optical microscope

Both keyboard and LCD are backlit for night-time use

Modular keyboard PCB -- customize layouts, add sensors, or swap in a touch surface

Audio with safe defaults

Integrated 0.7 W speaker for notifications

Vibration motor

3.5 mm headset jack

No integrated microphone -- audio surveillance is not possible when headset is unplugged

Integrated Wi-Fi

Sandboxed in a hardware-delineated untrusted domain

Silicon Labs WF200C chipset

USB Type-C port

Supports charging at 5 V; over-voltage protection tolerant to 20 V

Power negotiation to 5 V @ 1.5 A (source and sink)

Supports legacy USB 2.0 full-speed PHY

Basic DRP negotiation hardware support

1100 mAh Li-Ion battery

Approx. 100 hours standby with Wi-Fi + embedded controller + static display enabled

Approx. 700 mW "on-state" (most features enabled and active, backlight off) power draw, or 5.5 hours continuous use

Integrated gas gauge for more accurate battery life estimate

Full charge in about three hours

Runtime depends on user application

Anti-tamper features

User-sealable metal can for trusted components

Dedicated real-time clock (RTC) with basic clock integrity monitoring

Power monitors trip reset in case of power glitches

Always-on accelerometer/gyro to detect movement in standby

Support for instant secure erase via battery-backed AES key and self-destruct circuit

責(zé)任編輯：xj

原文標(biāo)題：便攜、安全、開源RISC-V SoC開發(fā)套件

文章出處：【微信公眾號：FPGA入門到精通】歡迎添加關(guān)注！文章轉(zhuǎn)載請注明出處。