輸入sel，clka，clkb，sel為1輸出clka，sel為0輸出clkb。

一、兩個(gè)時(shí)鐘源是倍數(shù)的關(guān)系

module Change_Clk_Source(
  input clk1,
  input clk0,
  input select,
  input rst_n,
  output outclk
);
  reg out1;
  reg out0;

  always @(negedge clk1 or negedge rst_n)begin
    if(rst_n == 1'b0)
      out1 <= 0;
    else
      out1 <= ~out0 & select;
  end

  always @(negedge clk0 or negedge rst_n)begin
    if(rst_n == 1'b0)
      out0 <= 0;
    else
      out0 <= ~select & ~out1;
  end

   assign outclk = (out1 & clk1) | (out0 & clk0);


endmodule

二、兩個(gè)時(shí)鐘源為異步時(shí)鐘的關(guān)系

module Change_Clk_Source(
  input clk1,
  input clk0,
  input select,
  input rst_n,
  output outclk
);
  reg out_r1;
  reg out1;
  reg out_r0;
  reg out0;


  always @(posedge clk1 or negedge rst_n)begin
    if(rst_n == 1'b0)
      out_r1 <= 0;
    else 
      out_r1 <= ~out0 & select;
  end


  always @(negedge clk1 or negedge rst_n)begin
    if(rst_n == 1'b0)
      out1 <= 0;
    else 
      out1 <= out_r1;
  end


  always @(posedge clk0 or negedge rst_n)begin
    if(rst_n == 1'b0)
      out_r0 <= 0;
    else 
      out_r0 <= ~select & ~out1;
  end

  always @(negedge clk0 or negedge rst_n)begin
    if(rst_n == 1'b0)
      out0 <= 0;
    else 
      out0 <= out_r0;
  end

  assign outclk = (out1 & clk1) | (out0 & clk0);




endmodule