先給大家分享一個(gè)測(cè)試設(shè)計(jì)的職位描述：

Job Function: Definition, architecture, modeling, verification, bring-up, debug and support of structural test for achievement of high defect coverage of microprocessor designs from product definition through production.

Responsibilities:

? Define, model and verify DFT features.
? Utilize industry-standard ATPG tools to generate patterns and verify them.
? Simulate/verify DFT patterns using Verilog VCS.
? Bring-up and debug DFT patterns on the ATE.
? Develop, implement and support DFT methodologies.
? Proficient with at-speed scan architectures, memory BIST and/or logic BIST.
? Proficient with coding/scripting using Perl.
? Mentor less senior DFT engineers and lead their efforts in achieving project objectives.
? Collaborate with engineering professionals across the company in order to advance the state of the art of DFT and test practices at AMD.

Preferred Experience:

? Master of EE or above. 4+ years DFT experience.
? Experience in microprocessor design or experience in handling complex SOC designs.
? Knowledgeable about industrial standards in DFT such as LBIST/JTAG/MBIST.
? Knowledgeable about ATE testers and ATPG standard practices.
? Expert knowledge of Verilog, RTL, Verilog simulators and waveform debugging tools.
? Good debugging capability with both RTL and gate-level simulations.
? Good communication skills and the ability to work with geographically distributed design sites.

可以看出要求很多。一些剛進(jìn)入電路行業(yè)的人會(huì)認(rèn)為測(cè)試相關(guān)的事情技術(shù)含量很低啊，當(dāng)然測(cè)試間的操作員是要做很多重復(fù)性勞動(dòng)。但是測(cè)試設(shè)計(jì)完全是另一回事。大些的企業(yè)里，測(cè)試設(shè)計(jì)工程師跟測(cè)試工程師是2個(gè)不同職位。前者主要負(fù)責(zé)制定測(cè)試策略，添加測(cè)試電路，生成測(cè)試向量，協(xié)助后者調(diào)通測(cè)試程序。后者主要在機(jī)臺(tái)上調(diào)通程序，處理量產(chǎn)中測(cè)試相關(guān)問(wèn)題，分析失效原因，協(xié)助其他工藝提高良品率。小點(diǎn)的公司可能2件事情同一個(gè)人做，或者干脆由管綜合的人做前者的事情，后者由工廠相關(guān)人員協(xié)助完成。由于大部分公司做的產(chǎn)品可靠性要求不高，所以很多時(shí)候只是在芯片上運(yùn)行一下功能測(cè)試的程序，不需要做全面的掃描，對(duì)測(cè)試設(shè)計(jì)的專業(yè)性也就沒(méi)那么高。另外很多公司甚至沒(méi)有量產(chǎn)經(jīng)歷，導(dǎo)致真正水平較高的測(cè)試設(shè)計(jì)人員很難找到。一般來(lái)說(shuō)做測(cè)試設(shè)計(jì)的人員都是有過(guò)一段時(shí)間邏輯電路設(shè)計(jì)經(jīng)驗(yàn)的，測(cè)試工程師大部分是半導(dǎo)體廠直接招的畢業(yè)生練出來(lái)的。如果有公司要染指利潤(rùn)，可靠性要求較高的汽車(chē)電子，航空電子，最重要的是要有夠水平的測(cè)試設(shè)計(jì)人員。

數(shù)字電路方面基本就這些崗位，模擬電路的崗位基本也就電路設(shè)計(jì)跟版圖設(shè)計(jì)，一個(gè)電路公司里邊如果有小妞，基本會(huì)出現(xiàn)在畫(huà)版圖的位置上，不過(guò)這些也基本是屌絲女，白富美基本不會(huì)光顧這種行業(yè)。下面看看這2種崗位的需求。

Position Description

Analog IC designer - responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.Background should demonstrate good problem solving skills, excellent analog aptitude, communication skills, and ability to work cooperatively in a team environment.The candidate would become part of analog IC design team creating leading edge IP (ADC's; DAC's; PLL's; SerDes) in leading edge processes (28nm and below).

Position Requirements

Must be familiar with design concepts for some basic analog functions including some of the following: data conversion, switched-capacitor circuits, op-amps, comparators, voltage and current references, phase-locked loops. Must be proficient in using CAD tools for circuit simulation, verification, and layout. 2-3 years employment or intern epxerience.Postion is also open to high performing recent EE graduate who has completed coursework that includes analog design.

版圖工程師

Key Areas of Responsibility:
? Technical tasks involved are full customer layout design， layout check and verification.

Required knowledge, skills, abilities:
? Understanding the basic process and device knowledge. It is preferred to have knowledge on HV process/device.
? Familiar with layout tools, verification tools, command file based on cadence environment.

Additional knowledge, skills, abilities, certifications:
? Understanding basic IC design knowledge, especially in analog IC. Knowing of ESD and latch-up related will be considered a plus.

Required education and experience:
? At least Bachelor degree is required. More than one year of prior experience in full-custom –design analog IC layout is necessary. Layout experience in Power management IC with HV process is preferred.

現(xiàn)在畫(huà)模擬版圖電路基本都是cds的輸入仿真工具，外加mentor的驗(yàn)證工具，現(xiàn)在模擬電路設(shè)計(jì)基本停留在cad階段，eda還處在概念期，所以對(duì)人員經(jīng)驗(yàn)要求較高。很多公司對(duì)有經(jīng)驗(yàn)的電路工程師的定義是8年以上，可見(jiàn)這個(gè)崗位成才挺慢。做模擬電路需要對(duì)電路理論，半導(dǎo)體制程都有些了解，如果做高頻電路，還要懂電磁波跟信號(hào)處理方面的東西，這些東西上大學(xué)期間不要說(shuō)學(xué)生能夠完全搞清楚的沒(méi)幾個(gè)，即使大部分教這些課程的叫獸僵尸，也只不過(guò)能把課本念熟練，真正完全理解的也不多見(jiàn)。所以真正有水平的模擬電路設(shè)計(jì)師，尤其是射頻集成電路設(shè)計(jì)的，即使世界范圍內(nèi)也是稀缺資源。當(dāng)然國(guó)內(nèi)現(xiàn)在也有不少在做模擬電路的，但是大部分是做電源管理芯片，這個(gè)大概算模擬電路中的入門(mén)產(chǎn)品吧，甚至有些小公司直接翻抄版圖，也能出些產(chǎn)品。整體來(lái)說(shuō)，這個(gè)崗位屬于需求大于供給的，即使水平一般，也不愁沒(méi)地方工作，除非鬧經(jīng)濟(jì)危機(jī)所有公司都裁員的時(shí)候。這個(gè)工作如果能把需要學(xué)的都完全搞明白了，其實(shí)勞動(dòng)量也就是算一下電路參數(shù)，做個(gè)仿真，指導(dǎo)一下版圖，屬于所有崗位里最輕松的，不過(guò)想能搞明白電路各種參量的關(guān)系，也絕非易事。

畫(huà)模擬版圖的貌似跟電路設(shè)計(jì)正好相反，很多新招聘的版圖員甚至不知道啥是三極管，然后被培訓(xùn)幾天后就練習(xí)抄版圖，然后熟練了逐漸自己設(shè)計(jì)。這個(gè)職位基本只要明白各層次之間關(guān)系，不是色盲，手腳夠快，基本就能很快上手。不過(guò)這個(gè)職位也是所有職位里邊最辛苦的，要看著花花綠綠的顯示器不停的調(diào)整各個(gè)線條，而且版圖設(shè)計(jì)時(shí)間壓力一般也很大。一些私營(yíng)公司的畫(huà)圖小妹甚至?xí)焕习辶R哭。這個(gè)職位可以說(shuō)是最有屌絲氣息的一崗位，當(dāng)然如果熬出來(lái)收入也還不錯(cuò)，只是這個(gè)活計(jì)實(shí)在太費(fèi)眼。

現(xiàn)在大部分電路都是數(shù)?；旌希酒嫌脭?shù)字設(shè)計(jì)流程，所以很多模擬電路設(shè)計(jì)都是設(shè)計(jì)模塊，然后集成進(jìn)芯片，由于模擬部分尚且沒(méi)有標(biāo)準(zhǔn)的驗(yàn)證流程，也不能像數(shù)字電路那樣放進(jìn)fpga先跑跑看，而且模擬電路的測(cè)試設(shè)計(jì)也沒(méi)有明確規(guī)范，所以集成在一起的芯片大部分問(wèn)題是由于模擬電路部分。相信隨著設(shè)計(jì)方法的改善與分工的細(xì)化，模擬電路方向會(huì)有更復(fù)雜的分工。

再來(lái)說(shuō)說(shuō)做數(shù)字后端版圖的大概情況

Job Description:
· Interface with IC Design/Verification team (timing and power constraints definition)
· Writing, running, optimization of logic and physical synthesis scripts
· In-depth knowledge of STA.Ablility to handle timing analysis for multiple modes and corners
· Physical design Floor planning, place & route, clock tree synthesis, routing cleanup
· Power IR & EM analysis
· Parasitic extraction/SPEF/SDF generation
· Physical Verification (DRC, ERC, LVS, ANTENNA)
· Deep understanding of DSM effects (sub 65 nm experience preferred)

Requirements:
· Masters/Bachelor’s Degree in Electrical/Electronics Engineering or in related field
· Tool skills:
· Synopsys Design Compiler
· PERL, TCL languages
· Prime Time and constraint creation/modification
· IR analysis tool such as PrimeRail, Redhawk
· Synopsys ICC experience preferred
· Calibre
· Ability to speak and write English is a must, CET 6
· Self-motivated team player and able to work with minimum supervision
· Minimum 3 years of physical design and timing closure experience
· Willingness to take overseas business trip

以上是一個(gè)數(shù)字版圖工程師的基本要求，現(xiàn)在大芯片后端綜合基本都用ICC，也有用SOC encounter的,版圖嚴(yán)重基本都是Calibre 這個(gè)工作除了要求熟練使用工具，掌握底層電路原理外，讀懂工藝文件，很需要一些耐心與細(xì)致的性格，因?yàn)橐话阕詣?dòng)生成的版圖未必能滿足所有時(shí)序要求，而且會(huì)有一些drc錯(cuò)誤，有時(shí)為了特殊目的也會(huì)做一些eco，這個(gè)就需要手工對(duì)版圖進(jìn)行一些編輯。面對(duì)滿眼的連線，要逐一修改切保證沒(méi)有失誤，是對(duì)體力與腦力的雙重考驗(yàn)。對(duì)這個(gè)工作崗位的要求其實(shí)也蠻高，不過(guò)由于其中一些雜活很耗費(fèi)體力，所以一般公司也會(huì)找新人幫忙做后端的打雜工，然后逐漸學(xué)習(xí)成長(zhǎng)。由于此類工具license基本是整個(gè)ic設(shè)計(jì)環(huán)節(jié)中最貴的，所以能有機(jī)會(huì)做后端綜合的人不太多，當(dāng)然開(kāi)的工資相對(duì)于邏輯設(shè)計(jì)也就屬于比較高的，這就相對(duì)于飛行員的工資比卡車(chē)司機(jī)高一樣。

當(dāng)然一般做后端設(shè)計(jì)的除了某些公司招聘的應(yīng)屆生逐漸上手的，還有一些是做手工版圖的后來(lái)轉(zhuǎn)行干這個(gè)，因?yàn)檫@個(gè)職位相對(duì)于全手工畫(huà)圖，工作量還是小一些的，而且聽(tīng)上去更高級(jí)一點(diǎn)。一旦開(kāi)始做這個(gè)東西，基本就沒(méi)有什么其他相關(guān)職位可以轉(zhuǎn)行去干了，做資深工程師是唯一選擇。

再說(shuō)說(shuō)仿真驗(yàn)證工程師的要求

Job Description:
Create verification plans for both block level and SoC level verification
Create testbenches in SystemVerilog with OVM/UVM
Utilize advanced verification techniques
Write tools and scripts in Perl and other script languages to enhance the verification process

Qualifications:
Experience with SystemVerilog and OVM/UVM
Experience with one or more simulators from the major EDA suppliers (Cadence, Mentor or Synopsys)
Experience with standard IP blocks and protocols such as Ethernet, TCP/IP, IPSec, iSCSI, DDR3, PCIe
Experience with advanced verification techniques like constrained random generation, functional coverage, assertions and formal verifiers
Experience with tools for regression management, configuration management and bug tracking
Good software skills in object oriented programming (OOP), C, C++, Perl, csh
Good problem solving
BS, MS or PhD in computer science or engineering

很久以前做數(shù)字電路的是沒(méi)有專門(mén)的驗(yàn)證工程師的，甚至現(xiàn)在小點(diǎn)的公司，這個(gè)任務(wù)也由做數(shù)字邏輯的兼任。不過(guò)現(xiàn)在大部分項(xiàng)目都是整合ip，驗(yàn)證的工作量反而更大一些，所以專門(mén)分離出來(lái)這個(gè)崗位。現(xiàn)在主流趨勢(shì)都是用SV的UVM,不過(guò)也有很多繼承之前項(xiàng)目的要用specman，當(dāng)然也有繼續(xù)用verilog寫(xiě)驗(yàn)證平臺(tái)的，整體來(lái)說(shuō)這個(gè)工作更適合之前習(xí)慣寫(xiě)C++的人來(lái)做，對(duì)于習(xí)慣了RTL代碼的人，需要些時(shí)間接受這些以前專門(mén)用在軟件開(kāi)發(fā)方面的思維方式。這個(gè)工作主要是設(shè)計(jì)驗(yàn)證平臺(tái)，驗(yàn)證用列并協(xié)同邏輯設(shè)計(jì)人員查找錯(cuò)誤。很多公司新招的畢業(yè)生都會(huì)先做幾天驗(yàn)證測(cè)試，跑跑仿真，這說(shuō)明這個(gè)工作是門(mén)檻比較低的，但是這個(gè)門(mén)檻低僅針對(duì)開(kāi)發(fā)驗(yàn)證用列，設(shè)計(jì)一個(gè)高效方便的驗(yàn)證平臺(tái)并不是很簡(jiǎn)單的事情，很多公司仍然沿用Verilog編寫(xiě)的驗(yàn)證環(huán)境，估計(jì)主要因?yàn)檎也坏饺四艽罱ㄒ粋€(gè)基于新方法學(xué)有效的驗(yàn)證環(huán)境。這個(gè)工作估計(jì)是電路設(shè)計(jì)崗位里邊最接近碼農(nóng)的，當(dāng)然也是需求人數(shù)最多的。這個(gè)崗位所開(kāi)的工資，從畢業(yè)生的6，7k到大忽悠的20k以上，都是可能的，當(dāng)然這個(gè)工作做成了領(lǐng)導(dǎo)，手下的人也是最多的。

電路公司里邊其他職位，基本都是跟軟件或者整個(gè)系統(tǒng)相關(guān)了，這里就先介紹這些吧。對(duì)于其他的，如果有人比較了解，歡迎補(bǔ)充。