SDR SDRAM Controller August 2002, ver. 1.1 1
M-WP-SDR-1.1 Introduction
The single data rate (SDR) synchronous dynamic random access memory (SDRAM) controller provides a simplified interface to industry standard SDR SDRAM. The SDR SDRAM Controller is available in either Verilog HDL or VHDL and is optimized for the Altera? APEX? architecture. The SDR SDRAM Controller supports the following
features:
■ Burst lengths of 1, 2, 4, or 8 data words
■ CAS latency of 2 or 3 clock cycles
■ 16-bit programmable refresh counter used for automatic refresh
■ 2-chip selects for SDRAM devices
■ Supports the NOP, READA, WRITEA, AUTO_REFRESH, PRECHARGE, ACTIVATE, BURST_STOP,
and LOAD_MR commands
■ Support for full-page mode operation
■ Data mask line for write operations
■ PLL to increase system performance
■ Support for data-path widths of 16, 32, and 64 bits
Figure 1 shows a system-level diagram of the SDR SDRAM Controller.