編者注：PCIE5.0已經(jīng)開始在產(chǎn)品中應(yīng)用，在下也參與了幾個PCIE5.0相關(guān)的項目，有系統(tǒng)級的，也有元器件級別的，在設(shè)計中確實也存在一些挑戰(zhàn)。比如在規(guī)范中也針對過孔設(shè)計做了說明。如下圖所示為PCIE5.0金手指Pad的設(shè)計示意圖。

本文是今年發(fā)布在DesignCon的文章，介紹了如何進行仿真和設(shè)計，以及過孔對系統(tǒng)的影響等等，最后結(jié)合仿真與測試，一并對比了前仿真、后仿真以及測量的結(jié)果，非常有參考意義，值得學(xué)習(xí)。

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Conclusion

? Extract Via EM models to a very high bandwidth:

o Since structures are small the extra simulation time from a denser FEM mesh is not a limiting factor. Yet the high stop frequency (80GHz) gave necessary extra resolution in the TDR response. This is important when comparing small differences between parameter values and deciding what effect if the adjustment of this parameter was trending in the right direction.

??Use more than one figure of merit:

oAn eye diagram alone is not enough to determine which via design is best, particular for small changes in ISI that may be compensated by Rx equalization. Instead, the key figures of merit during optimization were Insertion Loss, Return Loss, TDR, NEXT & FEXT, giving a rounded view of the behavior of the via or Via Array. Often, picking an optimal design that is practical to build is a challenging endeavor, but having multiple FOMs gives the designer confidence in their choice. Likewise, the final system simulation with equalized eye diagrams provides the final decision on whether the design, and full channel passes the spec. In the duration of this work, some figures of merit such as ‘Signal Spectrum at the Tx’ and ‘Signal Spectrum at the Rx’ were thrown away, as deemed not useful.

??What is worse? A lower via impedance due to excess capacitance, or a via that?transitions between capacitive & inductive?

oThis is difficult to predict from viewing the TDR alone, but having several figures of merit to rely on verified that having a much lower impedance due to excess capacitance was clearly worse.

? Laser Vias for highest speed:

o In all cases, the shortest via transitions were best if they can be practically applied.

? Take care of NEXT / FEXT:

o System simulations demonstrated that sub optimal design combinations could lead to >12dB increase in both NEXT and FEXT at Nyquist. In all cases though, these values were still well below the rule of thumb (< 20dB).

? Shared stitching vias in a Via Array?

o No. If you have space, it is best to provide separate stitching vias closest to the longest part of the via (Buried via in th is instance).

? Reference Models:

o A critical piece of the system validation process is access to a standard specific PCIe Gen5 IBIS AMI Rx model with adaptive EQ.

編輯：黃飛

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